ANT Forum

Yes, a HW SPI will work well with ANT byte synchronous mode. ANT is the master in the link. The SIMO, MISO and SCLK lines of the SPI port can be interfaced to SOUT, SIN and SCLK directly. The SS line of a traditional SPI port should NOT be used. Although similar in functionality to SEN, this control signal works a little differently in the ANT implementation and should be implemented using a GPIO. Other control lines should also be implemented using GPIOs.

Please refer to document D00000794, Interfacing with ANT General Purpose Chipsets and Modules for details.      

Hello,

I have a problem when using the HW SPI to communicate with a ANT CC2571.
- I have connected the SPI's MISO, MOSI and SCLK to ANT's SIN, SOUT and SCLK.
-I also connected the MCU's Host_MSG_Ready and Host_SRDY to ANT's SMSGRDY and SRDY.
-the ANT's Pin SEN is connected to one pin of MCU with a resistor 1Momhs pull-up as said in the document "Interfacing with ANT General Purpose Chipsets and Modules".
-I connected the others pins of ANT to make a communication byte-synchronous.

-to make a reset synchronous, I did:
-SMSGRDY = 1
-SRDY = 1
-wait 1ms
-SRDY = 0
-wait 300us
-SMSGRDY = 0
-wait 500ms
-while (SEN != 0) ; // wait for SEN = 0
-SRDY = 1
-to start communicate with ANT, I did:
-SMSGRDY = 0
-while (SEN != 0) ; // wait for SEN = 0
-SRDY = 0
-wait 6us
-SRDY = 1

And I have receive nothing from ANT ( normally I could have received 0xA4 or 0xA5 from ANT). My SPI use IT to detect the transmission of 8 bits

Did I do something wrong? Can somebody help me? Is there any method to test that the MCU is correctly communicated with ANT ?

Thanks for your helps

optimist_259      

Hi,

In synchronous mode ANT->Host always sends 0xA4. If you could send a timing diagram, that would be the best way to diagnose your problem. In the meantime, you could use the reset pin to hard reset your CC2571.

Best regards,
Harrison      

I can't give you the timing diagram but I think I have a problem with my SCLK signal. In fact, I must use resistances and transitors to convert signals from 5V to 3,3V and from 3,3V to 5V because my MCU use the source 5V. When I look at the ANT's SCLK signal, it is equal to 800mV when it is in Low stage (0 Logic). So when this signal pass through the transitor it is always equal to 5V (1 logic).

Is it normal that the SCLK signal is not equal to 0V when it is in Low stage (0 logic ?).      

800 mV is quite a bit higher than I would expect. When a signal goes low it should be pulled down to the same voltage as GND on the ANT, give or take some tolerance. Your level shifting logic may be introducing pull to the line.

Best regards,
Harrison      

Hello,

When using the HW SPI, my MCU has 4 four combinations of SCK phase and polarity:

Leading edge Trailing edge SPI mode

Sample (rising) Setup (falling) 0
Setup (rising) Sample (falling) 1
Sample (falling) Setup (rising) 2
Setup (falling) Sample (rising) 3

I would like to know which mode I should use to communicate between MCU and ANT ? Can anyone explain the different between "Sample" and "Setup" for me ?

Another question, is it right that in mode Byte Synchronous, the Sync Byte is always sent from ANT, and depend on this byte, we will sent the others bytes from MCU to ANT (case Sync Byte = 0xA5) or we will receive the rests from ANT to MCU (case sync Byte = 0xA4) ?

Thanks      

Hi,

Wikipedia has an excellent article on SPI clock polarity and phase found here. The timing diagrams in the "Interfacing with ANT General Purpose Chipsets and Modules" document (found here) show the data flow, where data should be transmitted on the falling edge of the clock (setup) and read on the rising edge of the clock (sampled). The base clock of ANT SPI is 1, so likely your SPI mode is 3.

The SYNC byte is only used to indicate the start of a message, with the message being of a variable length of bytes.
A Host->ANT message should look like [A5][LENGTH][ID][][]...[][CHECKSUM]
A ANT->Host message should look like [A4][LENGTH][ID][][]...[][CHECKSUM]

Best regards,
Harrison