ANT Forum

I am trying to send bytes from MSP430 microcontroller to ANT+ module (NRF51422) using SPI interface. On the manual it says that the SEN signal is typically high in the SPI mode and then once a message ready signal (MSGRDY) is asserted by the microcontroller, the SEN signal is pulled down by the ANT module and then the microcontroller starts sending data. However, in my case the SEN is always low and it is not affected by the changes on MSGRDY. So can anyone propose what could be wrong.
The module is programmed with the proper firmware and hex file for the ANT Network Processor Configuration.
Attached is the SPI interfacing guidelines based on which I took care of signals.      

As you are using an MSP430, I would strongly recommend that you look at the "ANT+ Embedded Reference Designs" on the downloads page. They contain updated serial drivers for the MSP430 you can build your application on.      

Thanks.
I am in the opinion of using my existing MSP430 microcontroller. It provides all necessary signals to establish an SPI connection with the ANT module. The problem is that the ANT module doesn't assert the SEN signal. I need to figure out why the ANT module is not doing what it should do.

Bests,
Ahmad      

Hi Ahmad,

Do you have a logic analyzer view of your signals?

The source code is written for the MSP430 microcontroller, so at least in my opinion it would be quite applicable for your system.

Cheers      

Hi,
Sorry for the delay. I have attached a snapshot of the scope for the singnals involved. I haven't included signals for MISO and MOSI as they aren't there until the hand shaking is not done.
Please note the glitch on the SRDY NOT signal and transition of SCLK from high to low when the MSGRDY NOT makes a transition from high to low. Also, the SEN NOT does not change at all at the transition.

Thanks,
Ahmad      

Is the application using the reset line or the reset message at device startup? This must be done at power on to ensure everything is synced before starting communication. From the diagram it looks like it's not using the reset message method though I'm not sure which snapshot in time it was taken.      

Yeah it is using the reset line as we cannot reset with reset message unless we have already established the channel. And the diagram shows a snapshot after the reset.      

Are you able to zoom in closer to the point of reset? Also to see when the lines when ANT asserts the SEN line? The very first message will be from ANT, when it sends the startup message.

If the MSP430 is controlling SRDY, why is there a glitch on the line? You may want to check the wiring for this.

If this image is heavily zoomed out, it kind of looks like that the SCLK did in fact assert itself as would be expected in Figure 3-4 in the interfacing document.

Just a note, you can always use the synchronous reset sequence, regardless of if the interface has been established, although I would recommend continuing to use the reset line.      

Hi,
I am attaching the zoomed version of the signals. Also, I included to the reset signal as well so you can see what happens next after the reset. "scope_1.bmp" shows the change of SEN only at the rising edge of the SLCK. Where the SLCK had gone down due to the reset. In "scope_3.bmp" I included the situation where MSGRDY signal is kept high and still the SEN signal shows the same behavior.

One programming issue that I am just noticing that I have is the delay loop which I think I should address that first. If you have a look at "scope_1.bmp", after reset, the MSGRDY goes low before the SCLK goes high whereas it needs to stay high until the SCL goes high again which is a sign of recovery from reset. I tried to make a delay loop to wait that amount of milliseconds, but it seems it doesn't affect at all. Following sequence of instructions are supposed to be executed:

P3OUT &= ~BIT0; // assert the reset pin (by making the pin 3.0 low)
P3OUT |= BIT0; // get out of reset (by making the pin 3.0 high)
for (int i = 0; i < 2000; i++); // wait until ANT module recovers (but it seems it doesn't do anything because for
// different values of i, I am getting the same delay of 35ms and I need a delay of
// 250ms).
P3OUT &= ~BIT3; // assert MSGRDY (by making pin 3.3 low)      

Hi,
So any clues on this problem?      

It's not clear from your images if the host controller is asserting SRDY after every byte. The original scope_0 picture indicates this may have happened once, but then the host never did it again.

As the first thing I expect after a reset is for ANT to send a startup message, SEN has stayed low indicating ANT wishes to send a message, and then the host should assert SRDY and not MESSAGE_READY to indicate to the network processor that it can begin sending the messages.      

So after the reset the microcontroller (host) should always expect to receive first before it can send regardless if the microcontroller needs that sent data from ANT module?      

I would just say that if the network processor wants to send data (by indicating with the write flag 0) then the host should accept processing that message first before attempting to send its own messages. The SPI can only work in 1 direction at a time.

It's just that at startup I would always expect ANT to want to send a message first (the startup message), thus it has asserted the SEN line on it's own. Before reset the SEN line behavior is undefined, so in this case it's coincidental that it looks like it stayed low.

Correct, regardless of whether or not you need the message, you need to receive all of them.      

D0 = SEN_NOT
D1 = SCLK
D2 = SRDY_NOT
D3 = MSGRDY_NOT
D4 = RESET_NOT

So after reset as you can see the module does not send out clock on D1 after D2 is asserted. There is only one glitch observed on the D1 which is the clock but as I zoomed in it is still only one glitch and not a stream of clock pulses. Please comment.      

Do you have a schematic of your design available? How have you set the configuration pins for SPI mode? The glitches you are seeing may indicate issues with the electrical connections.      

I am unable to attach a pdf of the schematic on this site. Is there any recommended file format that is acceptable on this site? or can I have your e-mail to send it over?

Thanks,