ANT Forum

Hi,

Could you provide timing diagrams of the serial lines on initialization and when attempting to communicate with the ANT Module? It is difficult to analyse the serial communication with just your word description.

In case you are not already using this resource, the primary document addressing serial communication with ANT modules is:

Interfacing with ANT General Purpose Chipsets and Modules (found under the Download Documents tab)


Regards,

Usama



     

Good Morning,

you're right, just writing a description isn't that suitable for my Problem. Please have a look at the attached screens.

C1 (yellow) => SMSGRDY
C2 (pink) => SEN
C3 (blue) => SRDY
C4 (green) => SCLK

1) Before and After a reset sequence SEN stays active (see Reset_1)
2) Before the Host-ANT transaction starts, I force SMSGRDY back to initial value (inactive)
3) I indicate a Host->ANT transaction by asserting SMSGRDY. Whilst SEN is still active, the SRDY-Pulse is directly send to ANT. Therefore I just get ONE SCLK-pulse (see Connect_1). SMSGRDY goes inactive
4) The action at point 3 is repeating 2 times (see Connect_all in the next post)
5) With the 4th cycle of this whole procedure, SEN goes inactive for the first time (see Connect_2)
6) With the 5th cycle, ANT-Chip becomes active after a short time and is sending once again just one sclk-pulse (see Connect_3 in the next post)      

The remaining screens (can only attach 3 files)      

Thanks for sending the sequence diagrams.

reset_1, connect_1, connect_2, connect_all:

I noticed that you assert the SRDY signal at the same time you assert SMSGRDY, before you receive the SEN pulse from the ANT module. If you refer to Figures 3-2 and 3-5 in the Interfacing with ANT General Purpose Chipsets and Modules Document, SRDY should be pulsed after asserting the SMSGRDY signal and after receiving the SEN signal..

For your reset, try asserting the SRDY signal after SEN has been asserted, that seems to be the primary difference between your communication and the diagram in the supporting document.      

The point is, that SEN is lowactive. As you can see in the diagrams it is always active (stays low) that's why the SRDY signal is send directly after the SMSGRDY signal. Cause he don't have to wait for SEN, it's already there.

If you have a look in connect_3 it works fine (in my point of view). I assert SMSGRDY, ANT takes a couple of us (220) to get awake, then the host asserts SRDY.


EDIT:
Problem almost solved with the help of http://www.thisisant.com/forum/viewthread/1254/#1308

I just don't know why the SEN# signal is toggling every 4th cycle, even when I want to send more data. For example:
In those 4 cycles I receive the sync(read) I write MSG_LENGHT (3+2) afterwards I send the MSG_ID and then the First of those 3 Data bytes. Immediately after the first Data byte (im in the 4th cycle now) ANT goes inactive! The remaining 2Databytes and the checksum won't be sent anymore.... I don't know what to do.